A resistive memory device, such as, for example, the electrically programmable resistive cross point memory device as described by Hsu et al., U.S. Patent Application Pub. No. 2003/0003674, is a non-volatile memory device that generally comprises an active layer capable of having its resistivity changed in response to an electrical signal, interposed between a plurality of conductive top and bottom electrodes. The active layer is usually made of a dielectric material, such as a colossal magnetoresistive (CMR) material or a high temperature superconducting (HTSC) material, which may be interposed between metal electrodes, for example, wire-shaped Pt-electrodes. At a cross point of a top electrode and a bottom electrode, a cross point referring to each position where a top electrode crosses a bottom electrode, the active layer has a programmable region with a resistivity that can change in response to an applied voltage. The memory effect of the resistive memory device lies in the voltage-controlled programming of the memory device into two distinct resistive states, related to the formation and disruption of a conductive filament through the programmable region. As the width of the conductive filament is believed to be in the range of nanometers, i.e., considerably smaller than the size of a resistive memory cell structure, the resistive memory device promises good scalability.
A resistive memory array, comprising a plurality of resistive memory elements, typically comprises a cross-bar array of top and bottom electrodes as illustrated in top view in FIG. 1, and in cross-section in FIG. 2. The resistive memory device 1 comprises a plurality of top electrodes (e.g., word lines WL) and a plurality of bottom electrodes (e.g., bit lines BL) which, together with an active layer 2 between the top and bottom electrodes, form a plurality of cross-point memory elements. The active layer 2 is substantially continuous, such that the active layer 2 extends across more than one cross point. The active layer 2 is interposed between the plurality of word lines WL and bit lines BL. At each crossing of a word line WL with a bit line BL, a programmable region, i.e., a bit 3, is formed in the active layer 2.
The resistivity of the bit 3 can be changed due to filament formation or filament disruption in response to a voltage applied between the corresponding word line WL and the bit line BL. The position of the filaments are schematically indicated with closed circles 4 in FIG. 1. Supposing that the world lines WL and the bit lines BL each have a width F being the minimum width obtainable with a given technology, the density of the resistive memory device 1 can be calculated to be 1 filament/4 F2, thus 1 bit/4 F2.